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flashrom v0.9.5.2-r1515 on Linux 3.6.6-gentoo (i686), built with libpci 3.1.10, GCC 4.5.4, little endian
flashrom is free software, get the source code at http://www.flashrom.org
 
Calibrating delay loop... OK.
Found chipset "Intel ICH5/ICH5R". Enabling flash write... OK.
Found SST flash chip "SST49LF002A/B" (256 kB, FWH) at physical address 0xfffc0000.
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Reading old flash chip contents... done.
Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x00000fff: 0xff1
ERASE FAILED!
Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x00003fff: 0x3fc8
ERASE FAILED!
FAILED!
Uh oh. Erase/write failed. Checking if anything changed.
Good. It seems nothing was changed.
Writing to the flash chip apparently didn't do anything.
This means we have to add special support for your board, programmer or flash chip.
Please report this on IRC at irc.freenode.net (channel #flashrom) or
mail flashrom@flashrom.org!